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ltc1773 1 1773fb applicatio s u descriptio u features typical applicatio u high efficiency: up to 95% constant frequency 550khz operation v in from 2.65v to 8.5v v out from 0.8v to v in opti-loop compensation minimizes c out synchronizable up to 750khz selectable burst mode operation low quiescent current: 80 a low dropout operation: 100% duty cycle secondary winding regulation soft-start current mode operation for excellent line and load transient response low shutdown i q = 10 a 1.5% reference accuracy precision 2.5v undervoltage lockout available in 10-lead msop the ltc 1773 is a current mode synchronous buck regu- lator controller that drives external complementary power mosfets using a fixed frequency architecture. the oper- ating supply range is from 2.65v to 8.5v, making it suitable for 1- or 2-cell lithium-ion battery powered appli- cations. burst mode operation provides high efficiency at low load currents. 100% duty cycle provides low dropout operation which extends operating time in battery-oper- ated systems. the operating frequency is internally set at 550khz, allow- ing the use of small surface mount inductors. for switch- ing-noise sensitive applications, it can be synchronized up to 750khz. peak current limit is user programmable with an external high side sense resistor. a sync/fcb control pin guarantees regulation of secondary windings regard- less of load on the main output by forcing continuous operation. burst mode operation is inhibited during syn- chronization or when the sync/fcb pin is pulled low to reduce noise and rf interference. soft-start is provided by an external capacitor. synchronous rectification increases efficiency and elimi- nates the need for a schottky diode, saving components and board space. the ltc1773 comes in a 10-lead msop package. cellular telephones rf pa supplies portable instruments wireless modems distributed power systems notebook and palm top computers, pdas single and dual cell lithium-ion powered devices synchronous step-down dc/dc controller figure 1. step-down converter high efficiency output current (ma) efficiency (%) 100 95 90 85 80 75 70 65 60 55 1 100 1000 5000 1773 f1b 10 l = sumida cdrh6d28-3r0 v in = 3.3v v in = 5v v in = 8v + + 30k 220pf 0.1 f c out 180 f c in 68 f l1 3 h v in 2.65v to 8.5v v out 2.5v r sense 0.025 ? 1773 f01 ltc1773 run/ss sync/fcb gnd sense v in tg i th v fb bg sw si9801dy 80.6k 169k 47pf protected by u.s. patents, including 5481178, 6580258, 6304066, 6127815. , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. opti-loop and burst mode are registered trademarks of linear technology corporation.
ltc1773 2 1773fb symbol parameter conditions min typ max units i vfb feedback current (note 4) 20 60 na v fb regulated feedback voltage (note 4) 0.788 0.80 0.812 v ? v ovl ? output overvoltage lockout ? v ovl = v ovl ?v fb 40 60 80 mv ? v fb reference voltage line regulation v in = 2.7v to 8.5v (note 4) 0.002 0.02 %/v v loadreg output voltage load regulation i th at 1.0v (note 4) 0.2 0.8 % i th at 0.6v (note 4) 0.2 0.8 % i s input dc bias current (note 5) normal mode v in = 5v, v ith = open, v sync/mode = open 400 600 a burst mode operation v ith = 0v, v in = 5v, v sync/mode = open 80 a shutdown v run/ss = 0v, 2.7v < v in < 8.5v 10 30 a shutdown v run/ss = 0v, v in < 2.4v 2 5 a v run/ss run/ss threshold 0.4 0.7 1.0 v i run/ss soft-start current source v run/ss = 0v 0.75 1.5 2.5 a v sync/fcb auxiliary feedback threshold v sync/fcb ramping negative 0.76 0.8 0.84 v i sync/fcb sync/fcb pull-up current v sync/fcb = 0v 0.1 0.4 1.0 a f osc oscillator frequency v fb = 0.8v 500 550 600 khz v fb = 0v 55 khz v uvlo undervoltage lockout v in ramping down from 3v 2.35 2.5 2.65 v v in ramping up from 0v 2.65 2.8 v ? vsense(max ) maximum current sense voltage 85 100 115 mv tg t r top gate drive rise time c load = 3000pf (note 6) 45 160 ns tg t f top gate drive fall time c load = 3000pf (note 6) 48 150 ns bg t r bottom gate drive rise time c load = 3000pf (note 6) 80 180 ns bg t f bottom gate drive fall time c load = 3000pf (note 6) 45 150 ns input supply voltage .............................. 0.3v to 10.0v i th voltage ................................................ 0.3v to 2.5v run/ss, v fb, sense voltages .................. 0.3v to v in sync/fcb voltage ...................................... 0.3v to v in bg, tg voltages...........................................0.3v to v in sw voltage ................................................... 5v to 11v operating ambient temperature range (note 2) ...............................................40 c to 85 c junction temperature (note 3) ............................. 125 c storage temperature range ..................65 c to 150 c lead temperature (soldering, 10 sec.)................. 300 c order part number t jmax = 125 c, ja = 120 c/w ltc1773ems absolute axi u rati gs w ww u package/order i for atio uu w (note 1) electrical characteristics ms part marking the denotes specifications which apply over the full operating temperature range, t a = 25 c. v in = 5v unless otherwise specified. ltmv 1 2 3 4 5 i th run/ss sync/fcb v fb gnd 10 9 8 7 6 sw sense v in tg bg top view ms package 10-lead plastic msop consult ltc marketing for parts specified with wider operating temperature ranges. order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/
ltc1773 3 1773fb note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc1773 is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the ?0 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: ltc1773: t j = t a + (p d ?120 c/w) note 4 : the ltc1773 is tested in a feedback loop which servos v fb to the balance point for the error amplifier (v ith = 0.8v) note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. note 6: rise and fall times are measured using 10% and 90% levels. electrical characteristics typical perfor a ce characteristics uw efficiency vs input voltage efficiency vs load current efficiency vs load current load regulation v in -v out dropout voltage vs load current input and shutdown currents vs input voltage output current (ma) 1 efficiency (%) 1773 g01 10 100 1000 5000 100 90 80 70 60 50 forced continuous v in = 5v v out = 2.5v see figure 1 burst mode operation sync(750khz) input voltage (v) efficiency (%) 100 95 90 85 80 75 2468 1773 g03 10 v out = 2.5v see figure 1 i out = 100ma i out = 1a load current (ma) 0 v in -v out (mv) 400 350 300 250 200 150 100 50 0 2000 1773 g05 500 1000 1500 2500 r sense = 0.025 ? v out = 1.8v si9801dy input voltage (v) 2 input current ( a) 10 1773 g06 4 6 8 500 450 400 350 300 250 200 150 100 50 0 sync to 750khz burst mode operation shutdown v out = 1.8v si9801dy r sense = 0.025 ? l = cdrh6d28-3ro output current (ma) 1 efficiency (%) 100 90 80 70 60 50 1773 g02 10 100 1000 v out = 2.5v see figure 1 v in = 5v v in = 3.3v v in = 8v 10,000 load current (a) 0 normalized v out (%) 0 0.05 0.10 0.15 0.20 0.25 0.30 1.5 2.5 1773 g16 0.5 1.0 2.0 3.0 3.5 r sense = 0.025 ? see figure 1
ltc1773 4 1773fb typical perfor a ce characteristics uw maximum current sense threshold vs v run/ss maximum current sense threshold vs temperature maximum current sense threshold vs v ith oscillator frequency vs temperature load step (burst mode operation) burst mode operation run/ss pin current vs temperature start-up load step (continuous mode) v run/ss (v) 0.5 maximum current sense threshold (mv) 120 100 80 60 40 20 0 2.0 3.0 1773 g07 1.0 1.5 2.5 3.5 4.0 temperature ( c) 80 1773 g08 ?0 0 40 60 20 20 60 140 120 100 maximum current sense threshold (mv) 100 105 95 85 temperature ( c) 60 ?0 ?0 frequency (khz) 540 550 100 120 80 40 1773 g10 530 520 0 20 60 140 560 temperature ( c) 60 ?0 ?0 run/ss current ( a) 1.5 2.0 100 120 80 40 1773 g11 1.0 0.5 0 20 60 140 2.5 1773 g12 i load = 100ma see figure 9 i l 500ma/div v out 20mv/div v in = 5v v out = 2.5v 20 s/div 1773 g13 i l 2a/div v run/ss 1v/div v out 2v/div v in = 5v v out = 2.5v 40ms/div see figure 9 1773 g14 i l 2a/div v out 100mv/div v in = 5v v out = 2.5v 100ma to 5a load step 100 s/div see figure 9 1773 g15 i l 2a/div v out 100mv/div v in = 5v v out = 2.5v 100ma to 5a load step 100 s/div see figure 9 v ith (v) maximum current sense threshold (mv) 1773 g09 120 100 80 60 40 20 0 0 0.4 0.8 1.0 0.2 0.6 1.2 1.4 1.6 burst mode operation forced continuous
ltc1773 5 1773fb i th (pin 1): error amplifier compensation point. the current comparator threshold increases with this control voltage. nominal voltage range for this pin is 0v to 1.2v. under high duty cycle and nearing current limit, i th can swing up to 2.4v. run/ss (pin 2): combination of soft-start and run control inputs. a capacitor to ground at this pin sets the ramp time to full current output. the time is approximately 0.8s/ f. forcing this pin below 0.4v shuts down all the circuitry. sync/fcb (pin 3): multifunction pin. this pin performs three functions: 1) secondary winding feedback input, 2) external clock synchronization and 3) burst mode opera- tion or forced continuous mode select. for secondary winding applications, connect to a resistive divider from the secondary output. to synchronize with an external clock, apply a ttl/cmos compatible clock with a fre- quency between 585khz and 750khz. to select burst mode operation, tie sync/fcb to v in . grounding this pin forces continuous operation. pi n fu n ctio n s uuu v fb (pin 4): feedback pin. receives the feedback voltage from an external resistive divider across the output. do not use more than 0.01 f of feedforward capacitance from fb to the output. gnd (pin 5): ground pin. bg (pin 6): bottom gate driver of external n-channel power mosfet. this pin swings from 0v to v in . tg (pin 7): top gate driver of external p-channel power mosfet. this pin swings from 0v to v in . v in (pin 8) : main supply pin. must be closely decoupled to gnd (pin 5). sense (pin 9): the negative input to the current com- parator. a sense resistor between this pin and v in sets the peak current in the top switch. connect this pin to the source of the external p-channel power mosfet. sw (pin 10): switch node connection to inductor. this pin connects to the drains of the external main and synchronous power mosfet switches. fu n ctio n al diagra uu w + run/soft start burst defeat freq shift switching logic and blanking circuit uvlo trip = 2.5v + 4 3 2 1 + + + + + sync/fcb x y osc i th v fb s q r q 0.22v 0.6v 0.8v ref anti shoot-thru 6 10 5 7 8 9 slope comp + 0.8v 0.86v 0.4 a shutdown run/ss 1.5 a ea run/ soft-start ovdet fcb i rcmp i comp 50mv 0.4v gnd sw bg tg v in sense sleep burst comp en 1773 fd y = ??only when x is a constant ? 0.8v sync defeat figure 2.
ltc1773 6 1773fb main control loop the ltc1773 uses a constant frequency, current mode step- down architecture to drive an external pair of comple- mentary power mosfets. during normal operation, the external top p-channel power mosfet turns on each cycle when the oscillator sets the rs latch, and turns off when the current comparator i comp resets the rs latch. the peak inductor current at which i comp resets the rs latch is controlled by the voltage on the i th pin, which is the output of error amplifier ea. the v fb pin, described in the pin functions section, allows ea to receive an output feedback voltage from an external resistive divider. when the load current increases, it causes a slight decrease in the feedback voltage relative to the 0.8v reference, which in turn causes the i th voltage to increase until the average inductor current matches the new load current. while the top p-channel mosfet is off, the bottom n-channel mosfet is turned on until either the inductor current starts to reverse, as indicated by the current reversal comparator i rcmp , or the beginning of the next cycle. the main control loop is shut down by pulling the run/ss pin low. releasing run/ss allows an internal 1.5 a current source to charge the external soft-start capacitor c ss . when c ss reaches 0.7v, the main control loop is enabled with the internal buffered i th voltage clamped at approximately 5% of its maximum value. as c ss contin- ues to charge, the internal buffered i th is gradually re- leased allowing normal operation to resume. an overvoltage comparator, 0v, guards against transient overshoots (>7.5%) as well as other more serious condi- tions that may overvoltage the output. in this case, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. burst mode operation the ltc1773 is capable of burst mode operation in which the external power mosfets operate intermittently based on load demand. to enable burst mode operation, simply allow the sync/fcb pin to float or connect it to a logic high. to disable burst mode operation and force continu- ous mode, connect the sync/fcb pin to gnd. the thresh- old voltage between burst mode operation and forced continuous mode is 0.8v. this can be used to assist in secondary winding regulation as described in auxiliary winding control using sync/fcb pin in the applications information section. when the converter operates in burst mode operation the peak current of the inductor is set to approximately a third of the maximum peak current value during normal opera- tion even though the voltage at the i th pin indicates a lower value. the voltage at the i th pin drops when the inductor? average current is greater than the load requirement. as the i th voltage drops below 0.22v, the burst compara- tor trips, causing the internal sleep line to go high and turn off both power mosfets. the circuit enters sleep mode with both power mosfets turned off. in sleep mode, the internal circuitry is partially turned off, reducing the quiescent current to about 80 a. the load current is now being supplied from the output capacitor. when the output voltage drops, causing i th to rise above 0.27v, the internal sleep line goes low, and the ltc1773 resumes normal operation. the next oscillator cycle will turn on the external top mosfet and the switch- ing cycle repeats. short-circuit protection when the output is shorted to ground, the frequency of the oscillator is reduced to about 55khz, 1/10 the nominal frequency. this frequency foldback ensures that the in- ductor current has more time to decay, thereby preventing runaway. the oscillator? frequency will gradually in- crease to 550khz after v fb rises above 0.4v. frequency synchronization the ltc1773 can be synchronized with an external ttl/ cmos compatible clock signal. the frequency range of this signal must be from 585khz to 750khz. do not synchronize the ltc1773 below 585khz as this may cause abnormal operation and an undesired frequency spec- trum. the top mosfet turn-on follows the rising edge of the external source. when the ltc1773 is clocked by an external source, burst mode operation is disabled; the ltc1773 then operates in pwm pulse skipping mode preventing current reversal. in this mode, when the output load is very low, current comparator i comp remains tripped for more than one cycle operatio u (refer to functional diagram)
ltc1773 7 1773fb the basic ltc1773 application circuit is shown in figure 1. external component selection is driven by the load requirement and begins with the selection of r sense . once r sense is known, l can be chosen, followed by the external power mosfets. finally, c in and c out are se- lected . r sense selection for output current r sense is chosen based on the required output current. the ltc1773 current comparator has a maximum thresh- old of 100mv/r sense . the current comparator threshold sets the peak of the inductor current, yielding a maximum and forces the main switch to stay off for the same number of cycles. increasing the output load current slightly, above the minimum required for discontinuous conduc- tion mode, allows constant frequency pwm. frequency synchronization is inhibited when the feedback voltage, v fb , is below 0.6v. this prevents the external clock from interfering with the frequency foldback for short-circuit protection. dropout operation when the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maxi- mum on-time. further reduction of the supply voltage forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. the output voltage will then be determined by the input voltage minus the ir voltage drop across the external p-channel mosfet, sense resistor, and the inductor. undervoltage lockout a precision undervoltage lockout shuts down the ltc1773 when v in drops below 2.5v, making it ideal for single lithium-ion battery applications. in shutdown, the ltc1773 draws only several microamperes, which is low enough to prevent deep discharge and possible damage to the lithium- ion battery that? nearing its end of charge. a 150mv hysteresis ensures reliable operation with noisy supplies. low supply operation the ltc1773 is designed to operate down to a 2.65v supply voltage. for proper operation at this low input voltage, sub-logic level mosfets are required. when the value of the output voltage is very close to the input voltage, the converter is running at high duty cycles or in dropout where the main switch is on continuously. see efficiency considerations in the applications information section. slope compensation and inductor peak current slope compensation provides stability by preventing subharmonic oscillations. it works by internally adding a ramp to the inductor current signal at duty cycles in excess of 30%. this causes the internal current comparator to trip earlier. the i th clamp level is also reached earlier than conditions in which the duty cycle is below 30%. as a result, the maximum inductor peak current is lower for v out /v in > 0.3 than when v out /v in < 0.3. to compensate for this loss in maximum inductor peak current during high duty cycles, the ltc1773 uses a patent pending scheme that raises the i th clamp level (proportional to the amount of slope compensation) when duty cycle is above 30%. operatio u (refer to functional diagram) applicatio n s i n for m atio n wu u u average output current i max equal to the peak value less half the peak-to-peak ripple current ? i l . allowing a margin for variations in the ltc1773 and external component values yields: r sense = 70mv/i max inductor value calculation the inductor selection will depend on the operating fre- quency of the ltc1773. the internal preset frequency is 550khz, but can be externally synchronized up to 750khz.
ltc1773 8 1773fb inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! molypermalloy (from magnetics, inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. a reasonable compromise from the same manu- facturer is kool m . toroids are very space efficient, especially when you can use several layers of wire. be- cause they generally lack a bobbin, mounting is more difficult. however, new designs for surface mount are available which do not increase the height significantly. power mosfet and schottky diode selection two external power mosfets must be selected for use with the ltc1773: a p-channel mosfet for the top (main) switch, and an n-channel mosfet for the bottom (syn- chronous) switch. the peak-to-peak gate drive levels are set by the v in voltage. therefore, for v in > 5v, logic-level threshold mosfets should be used. but, for v in < 5v, sub-logic level threshold mosfets (v gs(th) < 3v) should be used. in these applications, make sure that the v in to the ltc1773 is less than 8v because the absolute maximum v gs rating of the majority of these sub-logic threshold mosfets is 8v. selection criteria for the power mosfets include the ?n resistance r ds(on) , reverse transfer capacitance c rss , input voltage, maximum output current, and total gate charge. when the ltc1773 is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle = v out /v in synchronous switch duty cycle = (v in ?v out )/v in the mosfet power dissipations at maximum output current are given by: p v v ir kv i c f main out in max dson in max rss = () + () + ()( )( )() 2 2 1 applicatio n s i n for m atio n wu u u the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. however, oper- ating at a higher frequency generally results in lower efficiency because of external mosfet gate charge losses. the inductor value has a direct effect on ripple current. the ripple current, ? i l , decreases with higher inductance or frequency and increases with higher v in or v out . ? i fl v v v l out out in = ()( ) ? ? ? ? ? ? 1 1 (1) accepting larger values of ? i l allows the use of lower inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is 30% to 40% of i max . remember, the maximum ? i l occurs at the maximum input voltage. the inductor value also has an effect on burst mode operation. the transition to low current operation begins when the inductor current peaks fall to approximately 1/3 its original value. lower inductor values (higher ? i l ) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to increase. inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot af- ford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy, or kool m cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will in- crease. ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates ?ard? which means that inductance collapses abruptly when the peak design cur- rent is exceeded. this results in an abrupt increase in
ltc1773 9 1773fb rms capacitor current is given by: c required i i vvv v in rms max out in out in ? () [] 12 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant de- viations do not offer much relief. note that capacitor manufacturer? ripple current ratings are often based on 2000 hours of life. this makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there is any question. c out selection the selection of c out is driven by the required effective series resistance (esr). typically, once the esr require- ment is satisfied the capacitance is adequate for filtering. the output ripple ( ? v out ) is determined by: ?? v i esr fc l out out ? + ? ? ? ? ? ? 1 8 where f = operating frequency, c out = output capacitance and ? i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since ? i l increases with input voltage. with ? i l = 0.4i out(max) and allowing for 2/3 of the ripple due to esr, the output ripple will be less than 50mv at max v in assuming: c out required esr < 2 r sense c out > 1/(8fr sense ) the first condition relates to the ripple current into the esr of the output capacitance while the second term guaran- tees that the output voltage does not significantly dis- charge during the operating frequency period due to ripple current. the choice of using smaller output capacitance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low esr to maintain the ripple voltage at or below 50mv. p vv v ir sync in out in max ds on = () + () () 2 1 where is the temperature dependency of r ds(on) and k is a constant inversely related to the gate drive current. both mosfets have i 2 r losses while the topside p-channel equation includes an additional term for transition losses, which are highest at high input voltages. the synchronous mosfet losses are greatest at high input voltage or during a short-circuit when the duty cycle in this switch is nearly 100%. the term (1 + ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but = 0.005/ c can be used as an approximation for low voltage mosfets. c rss is usually specified in the mosfet characteristics. the constant k = 1.7 can be used to estimate the contributions of the two terms in the main switch dissipation equation. typical gate charge for the selected p-channel mosfet should be less than 30nc (at 4.5v gs ) while the turn-off delay should be less than 150ns. however, due to differ- ences in test and specification methods of various mosfet manufacturers, the p-channel mosfet ultimately should be evaluated in the actual ltc1773 application circuit to ensure proper operation. a schottky diode can be placed in parallel with the syn- chronous mosfet to improve efficiency. it conducts during the dead-time between the conduction of the two power mosfets. this prevents the body diode of the bottom mosfet from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency. a 1a schottky is generally a good size for 5a to 8a regulators due to the relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. the diode may be omit- ted if the efficiency loss can be tolerated. c in selection in continuous mode, the source current of the top mosfet is a square wave of duty cycle v out /v in . to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the maximum applicatio n s i n for m atio n wu u u
ltc1773 10 1773fb the i th pin opti-loop compensation components can be optimized to provide stable, high performance transient response regardless of the output capacitors selected. manufacturers such as nichicon, united chemicon and sanyo should be considered for high performance through- hole capacitors. the os-con semiconductor dielectric capacitor available from sanyo has the lowest esr/size ratio of any aluminum electrolytic at a somewhat higher price. once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple(p-p) requirement. in surface mount applications multiple capacitors may have to be paralleled to meet the esr or rms current handling requirements of the application. aluminum elec- trolytic and dry tantalum capacitors are both available in surface mount configurations. in the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. an excellent choice is the avx tps series of surface mount tantalum, available in case heights ranging from 2mm to 4mm. other capacitor types include sanyo os-con and poscap, nichicon pl series, panisonic sp series and sprague 593d and 595d series. consult the manufacturer for other specific recommenda- tions. output voltage programming the output voltage is set by a resistive divider according to the following formula: vv r r out =+ ? ? ? ? ? ? 08 1 2 1 . (2) the external resistive divider is connected to the output as shown in figure 3, allowing remote voltage sensing. applicatio n s i n for m atio n wu u u run/soft-start function the run/ss pin is a dual purpose pin that provides the soft-start function and a means to shut down the ltc1773. soft-start reduces surge currents from v in by gradually increasing the internal current limit. power supply se- quencing can also be accomplished using this pin. an internal 1.5 a current source charges up an external capacitor c ss . when the voltage on run/ss reaches 0.7v the ltc1773 begins operating. as the voltage on run/ss continues to ramp from 0.7v to 1.8v, the i th clamp is also ramped at a proportionally linear rate. depending on the external r sense used, the peak inductor current, and thus the internal current limit, rises with the run/ss voltage. the output current thus ramps up slowly, charging the output capacitor. if run/ss has been pulled all the way to ground, there will be a delay before the current starts increasing and is given by: t c a sfc delay ss ss == () 07 15 047 . . ./ pulling the run/ss pin below 0.4v puts the ltc1773 into a low quiescent current shutdown mode (i q < 10 a). this pin can be driven directly from logic as shown in figure 4. diode d1 in figure 4 reduces the start delay but allows c ss to ramp up slowly providing the soft-start function. this diode can be deleted if soft-start is not needed. figure 3. setting the ltc1773 output voltage ltc1773 v fb gnd r1 r2 1773 f03 0.8v v out 8.5v auxiliary winding control using sync/fcb pin the sync/fcb pin can be used as a secondary feedback to provide a means of regulating a flyback winding output. when this pin drops below its ground referenced 0.8v threshold, continuous mode operation is forced. in con- tinuous mode, the p-channel main and n-channel syn- chronous switches are switched continuously regardless of the load on the main output. figure 4. run/ss pin interfacing 3.3v or 5v run/ss run/ss c ss c ss d1 1773 f04
ltc1773 11 1773fb synchronous switching removes the normal limitation that power must be drawn from the inductor primary winding in order to extract power from auxiliary windings. with continuous synchronous operation, power can be drawn from the auxiliary windings without regard to the primary output load. the secondary output voltage is set by the turns ratio of the transformer in conjunction with a pair of external resistors returned to the sync/fcb pin as shown in figure 5. the secondary regulated voltage, v sec , in figure 5 is given by: vnvv v r r sec out diode ? + () ? >+ ? ? ? ? ? ? 1081 4 3 . where n is the turns ratio of the transformer and v out is the main output voltage sensed by v fb . although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc1773 circuits: v in quiescent current, external power mosfet gate charge current, i 2 r losses, and topside mosfet transition losses. 1. the v in quiescent current is due to the dc bias current as given in the electrical characteristics, it excludes mosfet driver and control currents. v in current results in a small loss which increases with v in . 2. the external mosfet gate charge current results from switching the gate capacitance of the external power mosfet switches. each time the gate is switched from high to low to high again, a packet of charge dq moves from v in to ground. the resulting dq/dt is the current out of v in ; it is typically larger than the dc bias current. in continuous mode, i gatechg = f(q t + q b ) where q t and q b are the gate charges of the external main and synchronous switches. both the dc bias and gate charge losses are proportional to v in and thus their effects will be more pronounced at higher supply volt- ages. 3. i 2 r losses are calculated from the resistances of the external r sense , the external power mosfets (r sw ) and the external inductor (r l ). in continuous mode, the average output current flowing through inductor l is ?hopped?between the main switch and the synchro- nous switch. thus, the series resistance looking into the sw pin from l is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc), as follows: r sw = (r ds(on)top +r sense ) ?dc + r ds(on)bot ?(1 ?dc) the r ds(on) for both the top and bottom mosfets can be obtained from the mosfet manufactures? datasheets. thus, to obtain i 2 r losses, simply add r sw and r l together and multiply their sum by the square of the average output current. 4. transition losses apply to the topside mosfet and increase when operating at high input voltages and higher operating frequencies. transition losses can be estimated from: transition loss = 2(v in ) 2 i o(max) c rss (f) applicatio n s i n for m atio n wu u u efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. efficiency can be expressed as: efficiency = 100% ?(l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percentage of input power. figure 5. secondary output loop connection ltc1773 + + r4 r3 1 f v out v sec c out l1 1:n sync/fcb bg sw tg 1773 f05 v in
ltc1773 12 1773fb bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to application note 76. a second, more severe transient is caused by switching in loads with large (>1 f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. the only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25)(c load ). thus a 10 f capacitor would require a 250 s rise time, limiting the charging current to about 200ma. minimum on-time considerations minimum on-time, t on(min) , is the smallest amount of time that the ltc1773 is capable of turning the top mosfet on and off again. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. the minimum on-time for the ltc1773 is about 250ns. low duty cycle and high frequency synchro- nous applications may approach this minimum on-time limit and care should be taken to ensure that: t v fv on min out in () < if the duty cycle falls below what can be accommodated by the minimum on-time, the ltc1773 will begin to skip cycles. the output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. if an application can operate close to the minimum on- time limit, an inductor must be chosen that has low enough inductance to provide sufficient ripple amplitude to meet the minimum on-time requirement. as a general rule, keep the inductor ripple current equal or greater than 30% of the i out(max) at v in(max). applicatio n s i n for m atio n wu u u other losses including c in and c out esr dissipative losses, and inductor core losses, generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to ( ? i load )(esr), where esr is the effective series resistance of c out . ? i load also begins to charge or dis- charge c out , which generates a feedback error signal. the regulator loop then returns v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing. opti-loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the availability of the i th pin not only allows optimization of control loop behavior but also provides a dc coupled and an ac filtered closed-loop response test point. the dc step, rise time and settling at this test point reflects the closed loop response. assuming a predominantly second order sys- tem, phase margin and/or damping factor can be esti- mated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the figure 1 circuit will provide an adequate starting point for most applications. the i th series r c -c c filter sets the dominant pole-zero loop compensation. the values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be decided upon because the various types and values determine the loop feedback factor gain and phase. an output current pulse of 20% to 100% of full load current having a rise time of 1 s to 10 s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. the initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/ dc ratio cannot be used to determine phase margin. the gain of the loop will be increased by increasing r c , and the
ltc1773 13 1773fb pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc1773. these items are also illustrated graphically in the layout diagram of figure 6. check the following in your layout: 1) are the signal and power grounds segregated? the ltc1773 signal ground consists of the resistive divider, the compensation network and c ss . the power ground consists of the (? plate of c in , the (? plate of c out , the source of the external synchronous nmos, and pin 5 of the ltc1773. the power ground traces should be kept short, direct and wide. connect the synchronous mosfets source directly to the input capacitor ground. 2) does the v fb pin connect directly to the feedback resistors? the resistive divider of r1 and r2 must be connected between the (+) plate of c out and signal ground. be careful locating the feedback resistors too far away from the ltc1773. the v fb line should not be routed close to any other nodes with high slew rates. 3) does the (+) terminal of c in connect to v in as closely as possible? this capacitor provides the ac current to the external power mosfets. 4) keep the switching nodes sw, tg and bg away from sensitive small-signal nodes, especially from the voltage and current sensing feedback pins. design example as a design example, assume the ltc1773 is used in a single lithium-ion battery powered cellular phone applica- tion. the v in will be operating from a maximum of 4.2v down to about 2.7v. the load current requirement is a maximum of 2a but most of the time it will be on standby mode, requiring only 2ma. efficiency at both low and high load currents is important. output voltage is 2.5v. with this information we can calculate r sense to be around 33m ? . for the inductor l, using equation (1), l fi v v v l out out in = ()( ) ? ? ? ? ? ? 1 1 ? (3) substituting v out = 2.5v, v in = 4.2v, ? i l = 800ma and f = 550khz in equation (3) gives: l v khz ma v v h = ? ? ? ? ? ? = 25 550 800 1 25 42 23 . () . . . a 2.5 h inductor works well for this application. for good efficiency choose a 4a inductor with less than 0.1 ? series resistance. c in will require an rms current rating of at least 1a at temperature and c out will require an esr of less than 0.066 ? . in most applications, the requirements for these capacitors are fairly similar. figure 6. ltc1773 layout diagram applicatio n s i n for m atio n wu u u 1773 f06 r1 r2 c in 1 2 3 4 5 10 9 8 7 6 r sense c c2 c c1 c out c ss r c v out + + v in bold lines indicate high current paths ltc1773 run/ss sync/fcb gnd sense v in tg i th v fb bg sw l1 + + q1 d1 q2
ltc1773 14 1773fb applicatio n s i n for m atio n wu u u for the selection of the external mosfets, the r ds(on) must be guaranteed at 2.5v since the ltc1773 has to operate down to 2.7v. this requirement can be met by the si9801dy. for the feedback resistors, choose r1 = 80.6k. r2 can then be calculated from equation (2) to be: figure 7. single lithium-ion to 2.5v/2a regulator r v r k use k out 2 08 1 1 171 169 = ? ? ? ? ? ? = . ? figure 7 shows the complete circuit along with its effi- ciency curve. 1773 f07a + 1 2 3 4 5 10 9 8 7 6 r sense 0.033 ? 33pf 200pf 0.1 f 30k v out 2.5v 2a 2.7v v in 4.2v + ltc1773 run/ss sync/fcb gnd sense v in tg i th v fb bg sw l1 2.5 h si9801dy c out 220 f 6.3v c in 150 f 6.3v 169k 1% 80.6k 1% c in : sanyo poscap 6tpa150m c out : avx tpsd227m006r0100 l1: cdrh5d28 r sense : irc lr1206-01-r033-f v in output current (ma) efficiency (%) 100 95 90 85 80 75 70 1 100 1000 5000 1773 f1b 10 v in = 3.3v v out = 2.5v efficiency curve for figure 7
ltc1773 15 1773fb typical applicatio n s u figure 8. dual output 2.5v/2a and 5v/100ma application i out (ma) 1 efficiency (%) 100 10000 100 95 90 85 80 75 70 65 60 1773 ? g17 10 1000 v in = 3.3v v in = 5v efficiency curve for figure 9 1773 ta01 + 1 2 3 4 5 10 9 8 7 6 r sense 0.033 ? 33pf 200pf 0.1 f 30k 169k 1% 80.6k 1% 422k 80.6k v out1 2.5v 2a v out2 5v 100ma 2.7v v in 8.4v + ltc1773 run/ss sync/fcb gnd sense v in tg i th v fb bg sw l1 5 h 1:1 si9801dy c out 220 f 6.3v + 22 f 6.2v mbr0530lt1 c in 100 f 10v c in : sanyo poscap 10tpa100m c out : avx tpsd227m006r0100 l1: coiltronics ctx5-4/bh electronics 511-0033 r sense : irc lr1206-01-r033-f 1773 ta02 + 1 2 3 4 5 10 9 8 7 6 r sense 0.015 ? 33pf 200pf 0.1 f 30k 169k 1% 80.6k 1% v out 2.5v 5a 2.7v v in 5.5v + ltc1773 run/ss sync/fcb gnd sense v in tg i th v fb v in bg sw l1 2.8 h c in 150 f 6.3v si9804dy si9803dy c out 220 f 6.3v 3 c in : sanyo poscap 6tpa150m c out : avx tpsd227m006r0100 l1: toko d104c 919as-2r8m r sense : dale wsl-2010 figure 9. single lithium-ion to 2.5v/5a regulator
ltc1773 16 1773fb 1773 ta03 + 1 2 3 4 5 10 9 8 7 6 r sense 0.025 ? 33pf 200pf 0.1 f 30k 249k 1% 80.6k 1% v out 3.3v 1a 2.7v v in 4.2v + ltc1773 run/ss sync/fcb gnd sense v in tg i th v fb bg sw l1 2 h l1 2 h c in 150 f 6.3v si9804dy si9803dy c out 220 f 6.3v 47 f + c in : sanyo poscap 6tpa150m c out : avx tpsd227m006r0100 l1: coiltronics ctx2-4/bh electronics 511-1010 r sense : irc lr1206-01-r033-f v in figure 10. single lithium-ion to 3.3v/1a synchronous zeta converter typical applicatio n s u output current (a) 0.001 efficiency (%) 100 90 80 70 60 50 40 30 20 0.01 0.1 1.0 1773 g18 v out = 3.3v v in = 2.7v v in = 5v v in = 3.3v v in = 4v efficiency curve for figure 10
ltc1773 17 1773fb typical applicatio n s u 1773 ta07 1 2 3 4 5 10 9 8 7 6 r sense 0.01 ? 47pf 220pf 0.1 f 0.1 f 1 f 0.01 f 30k 100k 1% 80.6k 1% 100pf v out2 3.3v 1a v out3 2.5v 150ma v out1 1.8v 6a 3.3v v in 6v ltc1773 run/ss sync/fcb gnd sense v in tg i th v fb bg sw t1 2.44 h 1:1 c in 150 f 6.3v c sec 47 f 6.3v si7540dp c out 680 f 4v 2 c in : panasonic special polymer c out : kemet t510687k004as t1: bh electronics 510-1007 r sense : irc lr2512-01-r010-j c sec : taiyo yuden lmk432f476zm 100pf d2* mbrs340t3 *note: d2 not necessary. if removed, efficiency drops by 1% + mbrm120t3 249k 1% 80.6k 1% lt1762-2.5 in shdn 8 5 out sense byp gnd 1 2 3 10 f + + figure 11. 750khz single lithium-ion to 2.5v/1a regulator figure 12. triple output 1.8v/6a, 2.5v/150ma,and 3.3v/1a application 1773 ta06 1 2 3 4 5 10 9 8 7 6 r sense 0.05 ? 47pf 220pf 0.1 f 0.1 f 30k 169k 1% 80.6k 1% 100pf v out 2.5v 1a 2.7v v in 4.2v ltc1773 run/ss sync/fcb gnd sense v in tg i th v fb bg sw c in 47 f 6.3v si6803dq 4.7 f 6.3v c out 47 f 6.3v c in , c out : sanyo poscap 6tpa47m l1: sumida cdrh5d28 3r0 r sense : irc lr1206-01-r050-j 100pf 750khz clk l1 3 h + +
ltc1773 18 1773fb 1773 ta08 1 2 3 4 5 10 9 8 7 6 r sense 0.01 ? 47pf 220pf 0.1 f 0.1 f 30k 100k 1% 80.6k 1% 100pf v out 1.8v 7a 2.7v v in 6v ltc1773 run/ss sync/fcb gnd sense v in tg i th v fb bg sw l1 1 h c in 150 f 6.3v si7540dp 4.7 f 6.3v c out 680 f 4v 2 c in : panasonic special polymer c out : kemet t510687k004as l1: toko type d104c 919as-1ron r sense : irc lr2512-01-r010-j 100pf d2* mbrs340t3 *note: d2 not necessary. if removed, efficiency drops by 1% + + 1773 ta05 1 2 3 4 5 10 9 8 7 6 r sense 0.068 ? 47pf 220pf 0.1 f 0.1 f 30k 118k 1% 80.6k 1% 100pf v out 2v 800ma 2.7v v in 6v ltc1773 run/ss sync/fcb gnd sense v in tg i th v fb bg sw l1 4.2 h c in 47 f 6.3v si9801dy 4.7 f 6.3v c out 47 f 6.3v c in , c out : sanyo poscap 6tpa47m l1: sumida cdrh5d28 4r2 r sense : irc lr1206-01-r068-f 100pf d2* mbr0530lt1 d1 mmsd914t1 *note: d2 not necessary. if removed, efficiency drops by 1% + + typical applicatio n s u figure 14. 3.3v to 1.8v/7a regulator figure 13. single lithium-ion to 2v/800ma regulator with current foldback
ltc1773 19 1773fb package descriptio u typical applicatio n s u 1773 ta09 1 2 3 4 5 10 9 8 7 6 r sense 0.04 ? 33pf 200pf 0.1 f 30k 100k 1% 80.6k 1% v out 1.8v 2a 4.5v v in 5.5v ltc1773 run/ss sync/fcb gnd sense v in tg i th v fb v in bg sw l1 2.5 h c in 47 f 10v si9942dy c out 47 f 10v c in , c out : taiyo yuden lmk550bj476mm l1: cdrh5d28 r sense : irc lr1206-01-r040-f figure 15. 5v to 1.8v/2a regulator with ceramic capacitors information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 0.53 0.152 (.021 .006) 0.18 (.007) 0.254 (.010) 0 ?6 typ detail ? detail ? gauge plane 5.23 (.206) min 3.20 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc msop (ms) 0603 seating plane 1.10 (.043) max 0.17 ?0.27 (.007 ?.011) typ 0.127 0.076 (.005 .003) 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max
ltc1773 20 1773fb part number description comments ltc1622 low voltage current mode step-down dc/dc controller v in : 2v to 10v, 550khz, burst mode operation, synchronizable ltc1627/ltc1707 low voltage, monolithic synchronous step-down regulator low supply voltage range: 2.65v to 8v, i out to 0.5a ltc1735 high efficiency synchronous step-down switching controller burst mode operation, 16-pin narrow so, fault protection ltc1735-1 high efficiency synchronous step-down switching controller output fault protection 16-pin gn, burst mode operation, power good ltc1771 low quiescent current step-down dc/dc controller v in : 2.8v to 18v, 10 a i q , ms8 package ltc1772/b sot-23 low voltage step-down controller 6-pin sot-23, 2v v in 10v, 550khz ltc1778 wide operating range/step-down controller, no r sense v in up to 36v, current mode, power good ltc1779 sot-23 current mode step-down converter 250ma output current, 2.5v v in 9.8v, up to 94% efficiency ltc1877 high efficiency monolithic synchronous step-down regulator v in from 2.65v to 10v, 10 a i q , 550khz, i out to 600ma,ms8 ltc1878 high efficiency monolithic synchronous step-down regulator v in from 2.65v to 7v, 10 a i q , 550khz, i out to 600ma,ms8 ltc3404 1.4mhz monolithic synchronous step-down regulator up to 95% efficiency, i out = 600ma at v in = 3.3v no schottky diode required, 8-lead msop linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 1106 rev b ? printed in usa related parts figure 16. dual output synchronous buck converter 1773 ta04 + 1 2 3 4 5 10 9 8 7 6 r sense 0.050 ? 33pf 200pf 0.1 f 0.1 f 30k 169k 1% 40.2k 1% v out1 2.5v 1a v out2 3.3v 500ma 4.5v v in 5.5v + ltc1773 run/ss sync/fcb gnd sense v in tg i th v fb bg sw l1 10 h 3:1 si6801dy c out1 150 f 6.3v + c out2 150 f 6.3v c in 150 f 6.3v c in , c out1 , c out2 : sanyo poscap 6tpa150m r sense : irc lr1206-01-r050-f d1: bas16 249k 1% si2302ds d1 47k v in u typical applicatio

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